INOS (IST-2002-507794)
Design, development and integration in VLSI of a H.264/AVC (MPEG-4) video encoder, using UMC library .18 process.
The H.264 VLSI encoder architecture supports real-time performance and it is compliant with the reference software encoder and specifically with the baseline profile 3.0 of the standard. The encoder can sustain an input throughput of 30 frames/sec of size 1024
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Paper Output
- K. Babionitakis, G. Doumenis, G. Georgakarakos, G. Lentaris, K. Nakos, D. Reisis, J. Sifnaios, N. Vlassopoulos, "A Real-Time H.264/AVC VLSI Encoder Architecture", Journal of Real-Time Image Processing, Issues 1-2, Volume 3, 2008, Springer
- K. Babionitakis, G. Lentaris, K. Nakos, D. Reisis, N. Vlassopoulos, G. Doumenis, G. Georgakarakos, J. Sifnaios, "An Efficient H.264 VLSI Advanced Video Encoder", pp. 545-548, December 2006, IEEE International Conference on Electronics, Circuits and Systems