Processor Architectures
DST is participating in the study and the development of a Super Scalar SPARC processor based on the SPARC V8 standard. The reserach on this topic has started in the University of Loughborough U.K by the team of professor Vassilios Chouliaras.
The SS SPARC design has been leveraged from Leon infrastructure. It involves a multi-issue, in order pipeline (6 stage) and full vector support. The micro-architecture hooks to extend for instantiating multiple machine contexts. The processor can be used in a configurable, extensible, CPU system by Instantiating multiple such CPUs on an AHB bus.
DST has focused on the study and the design of the Floating Point Unit (FPU) and the Load-Store Unit (LSU) involving the Data Cache, the level-1 and level-2 Cache and the Effective Address calculator.
Paper Output
- K. Manolopoulos, D. Reisis, V.A. Chouliaras, "An efficient multiple precision floating-point Multiply-Add Fused unit", MICROELECTRONICS JOURNAL, 49, pp.10-18, ISSN: 0026-2692, March 2016.
- V.A. Chouliaras, K. Manolopoulos, D. Reisis, "A Configurable Length, Fused Multiply-Add Floating Point Unit for a VLIW Processor", 22nd IEEE International Conference on Systems on Chip, Belfast, 2009
- D. Stevens, N. Glynn, P. Galiatsatos, V. Chouliaras, D. Reisis, "Evaluating the Performance of a Configurable, Extensible VLIW Processor in FFT Execution", IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2009
- V.A. Chouliaras. V.M. Dwyer, S. Agha, J.L. Nunez-Yanez, D. Reisis, K. Nakos. K. Manolopoulos, "Customization of an embedded RISC CPU with SIMD extensions for video encoding", pages:135-152, 2007, The VLSI Journal of Integration, Elsevier
- V. Chouliaras, T. Jacobs, J. Nunez-Yanez, K. Manolopoulos, K. Nakos, D. Reisis, "Thread Parallel MPEG-2 and MPEG-4 Encoders for Shared-Memory System-on-Chip Multiprocessors", International Journal of Computers and Applications, Issue 4, Volume 29, 2007, Acta Press