Processor Architectures

DST is participating in the study and the development of a Super Scalar SPARC processor based on the SPARC V8 standard. The reserach on this topic has started in the University of Loughborough U.K by the team of professor Vassilios Chouliaras

The SS SPARC design has been leveraged from Leon infrastructure. It involves a multi-issue, in order pipeline (6 stage) and full vector support. The micro-architecture hooks to extend for instantiating multiple machine contexts. The processor can be used in a configurable, extensible, CPU system by Instantiating multiple such CPUs on an AHB bus. 

DST has focused on the study and the design of the Floating Point Unit (FPU) and the Load-Store Unit (LSU) involving the Data Cache, the level-1 and level-2 Cache and the Effective Address calculator.

Paper Output